DSD 2009 Program: Keynote 2


Keynote DSD 2:
Dr. Jeroen Leijten, Co-Founder and Chief Technology Officer of Silicon Hive, Eindhoven, The Netherlands
Enabling the Next Major Step in Migrating Hardware Designs to Software
Prof. Jeroen Leijten has 15 years experience in parallel computer architectures and reconfigurable computing. At Silicon Hive he has been leading the development of Silicon Hive's parallel processing technology and related processor generation tools and libraries. Prior to co-founding Silicon Hive he was leading a next-generation processor architecture and software compiler codesign project in Philips Research. At Philips Research he has worked as a senior scientist within research groups focusing on digital VLSI and systems on silicon. In 1998 he obtained a Ph.D. degree in reconfigurable multiprocessor architectures for real-time digital signal processing applications from the Eindhoven University of Technology. Jeroen currently holds more than 10 US patents on processor architecture and related technology.
Abstract The continuous advances in CMOS technology provide improvements in area, speed and power dissipation for the same design when moving to the next technology node. This enables a continuous evolution of moving applications from hardware to software, as soon as a software solution becomes feasible. Choosing a software-based solution helps to reduce the number of silicon re-spins required and enables a parallel process of designing a System-on- Chip (SoC) wherein parallel teams work on integrating existing programmable processors and implementing the application in software. Moreover, SoCs based on programmable platforms have a longer product life cycle than their hardwired counterparts as they allow feature upgrades in software. Enabling the next major step in migrating applications from hardware to software, requires far more powerful, far more area-efficient, and far more powerefficient C-programmable processors than are available using conventional programmable approaches. This will enable efficient software implementations of applications, which up to now have been implemented in hardwired logic because of performance, cost and power constraints. To achieve a high level of computational efficiency in programmable processors two key measures must be taken. First, processors should focus on computing in parallel at modest clock rates. And second, control hardware overhead in processors should be minimized. Cprogrammable processors must combine multiple styles of parallelism and exhibit minimal control hardware overhead, all rightfully balanced towards the targeted application domain. Parallelism in computation must be matched with properly dimensioned parallelism in storage and I/O bandwidth. This means that rather than focus on a one-fits-all solution for different application domains, different programmable solutions must be tuned to different application domains to achieve the best possible balance between flexibility, performance, area and power for each domain. This keynote speech will discuss the challenges and commercially proven solutions to achieve the above, using Silicon Hive technology as an example. Underlying all Silicon Hive solutions is the same basic processor architecture template and associated re-targetable software development tool suite. Key to achieving efficiency is powerful processor specification exploration and generation technology as well as groundbreaking software compilation technology. These technologies were developed as one integrated whole, based on decades of research and development combining vast expertise in processor architecture, compilation technology, application knowledge, and hardware design. Because of this integrated approach, Silicon Hive is able to take scalability in parallelism far beyond established limits. The keynote speech will address the key elements of this integrated approach in more detail.


June 5th, 2009
The Conference Program and Keynotes information are available in the website.
May 26th, 2009
The deadline for author registration and submission of the camera ready paper is extended to June 5th, 2009.
May 8th, 2009
Registration to DSD2009 is now open.
March 30th, 2009
DSD2009 submission process is now closed.
For any issues, queries or problems concerning submission updates or uploadings please contact the PC Chair directly.

March 16th, 2009
The deadline for paper submission is extended to March 27th, 2009.