{"id":10020,"date":"2026-07-21T10:53:32","date_gmt":"2026-07-21T09:53:32","guid":{"rendered":"https:\/\/www.iuma.ulpgc.es\/?p=10020"},"modified":"2026-07-21T11:22:20","modified_gmt":"2026-07-21T10:22:20","slug":"seminarios-diseno-chips-tecnologias-tsmc","status":"publish","type":"post","link":"https:\/\/www.iuma.ulpgc.es\/en\/seminarios-diseno-chips-tecnologias-tsmc\/","title":{"rendered":"TSMC\u2019s FinFET 16N Technology Chip Design Seminars"},"content":{"rendered":"<p class=\"wp-block-paragraph\">IUMA Institute, within the training and dissemination activities of advanced technology design methodologies and techniques, has launched a series of free seminars for student training and PDI in the design of advanced integrated circuits in TSMC FinFET technology. These seminars are part of the participation of the IUMA in the EUROPRACTICE pilot programme in advanced technologies.<\/p>\n\n\n\n<div class=\"wp-block-group is-nowrap is-layout-flex wp-container-core-group-is-layout-8f761849 wp-block-group-is-layout-flex\">\n<p class=\"wp-block-paragraph\">This first session, held on July 15, was given by the Microelectronic Technology Division (TME) of the IUMA.  The session was oriented to design <em>full-custom<\/em>. Key aspects of TSMC\u2019s 16N TSMC technologies have been introduced in the first part of the session, including the architecture of transistors, process layers, particularities, capabilities and advantages of this FINFET technology over the planar nodes. Next, attendees are introduced to the TSMC 16N FinFETs design kit <em>full-custom<\/em>, detailing its components and libraries.<\/p>\n<\/div>\n\n\n\n<p class=\"wp-block-paragraph\">The second half of the session had a more practical approach (<em>hand-ons<\/em>), serving as a direct introduction to schematic design by using design tools professions, Cadence Virtuoso. The characterization of a FinFET transistor was carried out, obtaining and analyzing its I-V curves, a fundamental step to understand its physical behavior and the particularities that the transistor presents. Finally, robust design techniques were proposed, with the realization of different simulations of <em>corners<\/em> of the process (min-max conditions) and a statistical analysis of Monte Carlo was performed. New sessions are planned for the <em>full-custom design<\/em> until completing the circuit layout and physical verification<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">A forthcoming seminar to be given by the IUMA SICAD Division will address the design <em>semicustom,<\/em> where the complete layout of a standard cell-based integrated circuit of the TSMC FinFET 16N library will be made from its description in a hardware description language (HDL). In this case different ASIC design techniques will be used, including simulation, logical synthesis and physical design using tools for <em>placement and route.\u00a0<\/em><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Those interested in attending this seminar should contact with <a href=\"mailto:carballo@iuma.ulpgc.es\">carballo@iuma.ulpgc.es<\/a> for additional information.<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"576\" src=\"https:\/\/www.iuma.ulpgc.es\/wp-content\/uploads\/2026\/07\/20260715_115832-r-1024x576.jpg\" alt=\"\" class=\"wp-image-10024\" srcset=\"https:\/\/www.iuma.ulpgc.es\/wp-content\/uploads\/2026\/07\/20260715_115832-r-1024x576.jpg 1024w, https:\/\/www.iuma.ulpgc.es\/wp-content\/uploads\/2026\/07\/20260715_115832-r-300x169.jpg 300w, https:\/\/www.iuma.ulpgc.es\/wp-content\/uploads\/2026\/07\/20260715_115832-r-768x432.jpg 768w, https:\/\/www.iuma.ulpgc.es\/wp-content\/uploads\/2026\/07\/20260715_115832-r-1536x864.jpg 1536w, https:\/\/www.iuma.ulpgc.es\/wp-content\/uploads\/2026\/07\/20260715_115832-r-2048x1153.jpg 2048w, https:\/\/www.iuma.ulpgc.es\/wp-content\/uploads\/2026\/07\/20260715_115832-r-18x10.jpg 18w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>","protected":false},"excerpt":{"rendered":"<p>El IUMA, dentro de las actividades de formaci\u00f3n y difusi\u00f3n de las metodolog\u00edas y t\u00e9cnicas de dise\u00f1o de tecnolog\u00edas avanzadas ha puesto en marcha una serie de seminarios gratuitos para la formaci\u00f3n de estudiantes y PDI en el dise\u00f1o de circuitos integrados avanzados en tecnolog\u00eda FinFET de TSMC. Estos seminarios se enmarcan dentro de la [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":10026,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[18,14,1],"tags":[116,117,86,115],"class_list":["post-10020","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-noticias","category-noticias-recientes","category-uncategorized","tag-asic","tag-sicad","tag-tme","tag-tsmc"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v28.0 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Seminarios sobre dise\u00f1o de chips en tecnolog\u00edas FinFET 16N de TSMC - Instituto Universitario de Microelectr\u00f3nica Aplicada<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.iuma.ulpgc.es\/en\/seminarios-diseno-chips-tecnologias-tsmc\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Seminarios sobre dise\u00f1o de chips en tecnolog\u00edas FinFET 16N de TSMC - Instituto Universitario de Microelectr\u00f3nica Aplicada\" \/>\n<meta property=\"og:description\" content=\"El IUMA, dentro de las actividades de formaci\u00f3n y difusi\u00f3n de las metodolog\u00edas y t\u00e9cnicas de dise\u00f1o de tecnolog\u00edas avanzadas ha puesto en marcha una serie de seminarios gratuitos para la formaci\u00f3n de estudiantes y PDI en el dise\u00f1o de circuitos integrados avanzados en tecnolog\u00eda FinFET de TSMC. Estos seminarios se enmarcan dentro de la [&hellip;]\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.iuma.ulpgc.es\/en\/seminarios-diseno-chips-tecnologias-tsmc\/\" \/>\n<meta property=\"og:site_name\" content=\"Instituto Universitario de Microelectr\u00f3nica Aplicada\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/IUMA.ulpgc\" \/>\n<meta property=\"article:published_time\" content=\"2026-07-21T09:53:32+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2026-07-21T10:22:20+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/www.iuma.ulpgc.es\/wp-content\/uploads\/2026\/07\/20260715_115832-scaled.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"2560\" \/>\n\t<meta property=\"og:image:height\" content=\"1441\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"wordpress\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@iumanews\" \/>\n<meta name=\"twitter:site\" content=\"@iumanews\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"wordpress\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"3 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.iuma.ulpgc.es\\\/seminarios-diseno-chips-tecnologias-tsmc\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.iuma.ulpgc.es\\\/seminarios-diseno-chips-tecnologias-tsmc\\\/\"},\"author\":{\"name\":\"wordpress\",\"@id\":\"https:\\\/\\\/www.iuma.ulpgc.es\\\/en\\\/#\\\/schema\\\/person\\\/37a33ecac9f83ab10f19329140aca8d8\"},\"headline\":\"Seminarios sobre dise\u00f1o de chips en tecnolog\u00edas FinFET 16N de TSMC\",\"datePublished\":\"2026-07-21T09:53:32+00:00\",\"dateModified\":\"2026-07-21T10:22:20+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.iuma.ulpgc.es\\\/seminarios-diseno-chips-tecnologias-tsmc\\\/\"},\"wordCount\":432,\"image\":{\"@id\":\"https:\\\/\\\/www.iuma.ulpgc.es\\\/seminarios-diseno-chips-tecnologias-tsmc\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/www.iuma.ulpgc.es\\\/wp-content\\\/uploads\\\/2026\\\/07\\\/20260715_115832-scaled.jpg\",\"keywords\":[\"ASIC\",\"SICAD\",\"TME\",\"TSMC\"],\"articleSection\":[\"Noticias\",\"Noticias Recientes\"],\"inLanguage\":\"en-US\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.iuma.ulpgc.es\\\/seminarios-diseno-chips-tecnologias-tsmc\\\/\",\"url\":\"https:\\\/\\\/www.iuma.ulpgc.es\\\/seminarios-diseno-chips-tecnologias-tsmc\\\/\",\"name\":\"Seminarios sobre dise\u00f1o de chips en tecnolog\u00edas FinFET 16N de TSMC - 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