{"id":49,"date":"2015-07-14T12:59:09","date_gmt":"2015-07-14T12:59:09","guid":{"rendered":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/?page_id=49"},"modified":"2017-07-31T12:57:57","modified_gmt":"2017-07-31T12:57:57","slug":"conference-papers","status":"publish","type":"page","link":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/publicaciones\/conference-papers","title":{"rendered":"Conference papers"},"content":{"rendered":"

DC self-heating in GaN on Si MOS-HEMTs<\/strong><\/em>
\nWorkshop on Compound Semiconductor Devices and Integrated Circuits held in Europe. WOCSDICE 2017
\nLas Palmas de Gran Canaria, Espa\u00f1a
\nInstituto Universitario de Microeelctr\u00f3nica Aplicada. Universidad de Las Palmas de Gran Canaria
\nR. Rodr\u00edguez, B. Gonz\u00e1lez, J. Garc\u00eda and A. Nunez<\/p>\n

DC characteristics with substrate temperature for GaN on Si MOS-HEMTs<\/strong><\/em>
\n11th Spanish Conference on Electron Device
\nBarcelona, Espa\u00f1a 2017
\nUniversidad de Barcelona
\nRa\u00fal Rodr\u00edguez del Rosario; Benito Gonz\u00e1lez P\u00e9rez; Javier Garc\u00eda Garc\u00eda; Aurelio Vega Mart\u00ednez<\/p>\n

DC SHEs on GaN HEMTs varying substrate material<\/em><\/strong>
\nX Conferencia de Dispositivos Electr\u00f3nicos CDE
\nAranjuez, Espa\u00f1a 2015
\nUniversidad Rey Juan Carlos
\nRa\u00fal Rodr\u00edguez del Rosario; Benito Gonz\u00e1lez P\u00e9rez; Javier Garc\u00eda Garc\u00eda; Antonio Nunez Ordonez; Fetene Mulugeta Yigletu; Benjam\u00edn \u00cd\u00f1iguez; Jos\u00e9 M. Tirado.<\/p>\n

Numerical Simulation and Compact Physical Modeling of AlGaN\/GaN Power HEMTs<\/em><\/strong>
\n Accounting for Mitigation of SHE Degradation by Using Engineered Substrate Materials<\/em><\/strong>
\nThe International Workshop on Nitride Semiconductors (IWN)
\nWroc\u0142aw, Polonia 2014
\nInstitute of High Pressure Physics \u00bb Unipress\u00bb PAS, University of Wroc\u0142aw, Wroc\u0142aw
\nResearch Centre EIT+, Institute of Low Temperatures and Structural Research PAS, Wroc\u0142aw
\nWroc\u0142aw, Polonia
\nRa\u00fal Rodr\u00edguez del Rosario; Benito Gonz\u00e1lez P\u00e9rez; Javier Garc\u00eda Garc\u00eda; F. Mulugeta; Jos\u00e9 Mar\u00eda Tirado; Benjam\u00edn \u00cd\u00f1iguez<\/p>\n

Integrated varactor modeling for a PN doughnut structure<\/em><\/strong>
\nXXVIII Design of Integrated Circuits and Systems Conference DCIS2013
\nSan Sebasti\u00e1n, Pa\u00eds Vasco, Espa\u00f1a 2013
\nUniversidad de Navarra
\nMargarita Marrero Mart\u00edn; Javier Garc\u00eda Garc\u00eda; Benito Gonz\u00e1lez P\u00e9rez; Ra\u00fal Rodr\u00edguez del Rosario; Antono Hern\u00e1ndez Ballester.
\n\u00abProceeding of XXVIII Design of Integrated Circuits and Systems Conference DCIS2013\u00bb.<\/p>\n

Study of Rectifiers for RFID tags using SOI<\/em><\/strong>
\nXXVIII Design of Integrated Circuits and Systems Conference DCIS2013
\nSan Sebasti\u00e1n, Pa\u00eds Vasco, Espa\u00f1a 2013
\nUniversidad de Navarra
\nRa\u00fal Rodr\u00edguez del Rosario; Benito Gonz\u00e1lez P\u00e9rez; Javier Garc\u00eda Garc\u00eda; Margarita Marrero Mart\u00edn; Antono Hern\u00e1ndez Ballester.
\n\u00abProceeding of XXVIII Design of Integrated Circuits and Systems Conference DCIS2013\u00bb.<\/p>\n

Study of RFID with SOI technology for UWB<\/em><\/strong>
\nIX Conferencia de Dispositivos Electr\u00f3nicos CDE
\nValladolid, Espa\u00f1a 2013
\nUniversidad de Valladolid
\nRa\u00fal Rodr\u00edguez del Rosario; Benito Gonz\u00e1lez P\u00e9rez; Javier Garc\u00eda Garc\u00eda; Margarita Marrero Mart\u00edn; Antonio Hern\u00e1ndez Ballester.<\/p>\n

Rectennas design using DG-MOSFETs<\/em><\/strong>
\nSPIE Microtechnologies 2013 (VLSI Circuits and Systems)
\nGrenoble, Francia 2013
\nRa\u00fal Rodr\u00edguez del Rosario; benito Gonz\u00e1lez P\u00e9rez; Javier Garc\u00eda Garc\u00eda; Margarita Marrero Mart\u00edn; Antonio Hern\u00e1ndez Ballester.
\n\u00abSPIE Microtechnologies 2013 (VLSI Circuits and Systems)\u00bb.<\/p>\n

Circuit models for PN integrated varactors<\/em><\/strong>
\nVIII Conferencia de Dispositivos Electr\u00f3nicos (Nacional)
\nPalma de Mallorca, Espa\u00f1a, 2011
\nM. Marrero; J. Garc\u00eda; B. Gonz\u00e1lez; A. Hern\u00e1ndez.
\n\u00abVIII Conferencia de Dispositivos Electr\u00f3nicos<\/p>\n

Coupled varactor based on PN junction and accumulation MOS for RF applications<\/em><\/strong>
\nVIII Conferencia de Dispositivos Electr\u00f3nicos (Nacional)
\nPalma de Mallorca, Espa\u00f1a, 2011
\nJ. Garc\u00eda; M. Marrero; B. Gonz\u00e1lez; I. Aldea; A. Hern\u00e1ndez. \u00abVIII Conferencia de Dispositivos Electr\u00f3nicos<\/p>\n

Effect of separation and depth of N+ diffusions in the quality factor and tuning range of PN varactors<\/em><\/strong>
\nSPIE Microtechnologies 2011 (VLSI Circuits and Systems)
\nPrague, Rep\u00fablica Checa 2011
\nMargarita Marrero Mart\u00edn; Tomasz Szydzik; Benito Gonz\u00e1lez P\u00e9rez; Javier Garc\u00eda Garc\u00eda; Antonio Hern\u00e1ndez Ballester.
\n\u00abProceeding of SPIE Microtechnologies 2011 (VLSI Circuits and Systems)\u00bb.<\/p>\n

Integrated PN Varactors and their Application in Wide Range VCOs<\/em><\/strong>
\nXXV Conference on Design of Circuits and Integrated Systems, DCIS 2010.
\nLanzarote, Spain. 2010
\nM. Marrero; B. Gonz\u00e1lez; J. Garc\u00eda; S. L. Khemchandani; A. Hern\u00e1ndez; J. del Pino. \u00abXXV Conference on Design of Circuits and Integrated Systems, DCIS 2010\u00bb. 2010.<\/p>\n

Capacitance estimation of PN varactors based on unit cells<\/em><\/strong>
\nVII Conferencia de Dispositivos Electr\u00f3nicos (Nacional)
\nSantiago de Compostela, 2009
\nM. Marrero; B. Gonz\u00e1lez; J. Garc\u00eda; A. Hern\u00e1ndez.
\n\u00abVII Conferencia de Dispositivos Electr\u00f3nicos<\/p>\n

Equivalent circuit model for capacitances in PN varactors with buried layer<\/em><\/strong>
\nVII Conferencia de Dispositivos Electr\u00f3nicos (Nacional)
\nSantiago de Compostela, 2009
\nM. Marrero; J. Garc\u00eda; B. Gonz\u00e1lez; A. Hern\u00e1ndez.
\n\u00abVII Conferencia de Dispositivos Electr\u00f3nicos<\/p>\n

A physical-based method for parameter extraction of on-chip spiral inductor<\/em><\/strong>
\nVI Conferencia de Dispositivos Electr\u00f3nicos (Nacional)
\nSan Lorenzo de El Escorial, 2007
\nA. Go\u00f1i; J. del Pino; J. Garc\u00eda; B. Gonz\u00e1lez; S. L. Khemchandani; A. Hern\u00e1ndez.
\n\u00abVI Conferencia de Dispositivos Electr\u00f3nicos (Nacional).\u00bb. 2007.<\/p>\n

A study of staked and miniature three-dimensional inductor performance for RF IC design<\/em><\/strong>
\nSPIE – The International Society for Optical Engineering\u2019s III International
\nSymposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference). Maspalomas, Las Palmas, Espa\u00f1a. 2007
\nA. Go\u00f1i; J. del Pino; S. L. Khemchandani; J. Garc\u00eda; B. Gonz\u00e1lez; A. Hern\u00e1ndez. \u00abSPIE – The International
\nSociety for Optical Engineering\u2019s III International Symposium on Microtechnologies for the New Millennium
\nDesign (VLSI Circuits and Systems Conference). Maspalomas, Las Palmas, Espa\u00f1a. 2007\u00bb. 2007.<\/p>\n

Analysis of PN Integrated Varactors with N+ Buried Layer varying P+ diffusions contour for RF Applications<\/em><\/strong>
\nXXII Conference on Design of Circuits and Integrated Systems, DCIS 2007. Sevilla, Espa\u00f1a. 2007
\nJ. Garc\u00eda; B. Gonz\u00e1lez; M. Marrero; I. Aldea; J. del Pino; A. Hern\u00e1ndez.
\n\u00abXXII Conference on Design of Circuits and Integrated Systems, DCIS 2007. Sevilla, Espa\u00f1a. 2007\u00bb. 2007.<\/p>\n

Influence of gate geometry in integrated MOS varactors on accumulation mode for RF<\/strong><\/em>
\nVI Conferencia de Dispositivos Electr\u00f3nicos
\nSan Lorenzo de El Escorial, 2007
\nE. Amselem; B. Gonz\u00e1lez; J. Garc\u00eda; I. Aldea; M. Marrero; A. Go\u00f1i; J. del Pino; S. L. Khemchandani; A. Hern\u00e1ndez.
\n\u00abVI Conferencia de Dispositivos Electr\u00f3nicos\u00bb. 2007.<\/p>\n

Influence of the diffusion geometry on PN Integrated Varactors<\/em><\/strong>
\nSPIE – The International Society for Optical Engineering\u2019s III International
\nSymposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference). Maspalomas, Las Palmas, Espa\u00f1a. 2007
\nJ. Garc\u00eda; B. Gonz\u00e1lez; M. Marrero; I. Aldea; J. del Pino; A. Hern\u00e1ndez. \u00abSPIE – The International Society for Optical Engineering\u2019s III International Symposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference). Maspalomas, Las Palmas, Espa\u00f1a. 2007\u00bb. 2007.<\/p>\n

A Method to Build-up an Integrated Inductor Library<\/em><\/strong>
\nXX Design of Integrated Circuits and Systems Conference
\nLisboa, Portugal, 2005
\nO. Medina; J. del Pino; A. Go\u00f1i; S. L. Khemchandani; J. Garc\u00eda; A. Hern\u00e1ndez.
\n\u00abXX Design of Integrated Circuits and Systems Conference.\u00bb. 2005.<\/p>\n

A Synthesizer for WLAN with a Fully Integrated VCO in 0,35 \u03bcm SiGe Technology<\/em><\/strong>
\nXX Design of Integrated Circuits and Systems Conference
\nLisboa, Portugal, 2005
\nS. L. Khemchandani; A. Go\u00f1i; J. del Pino; B. Gonz\u00e1lez; J. Garc\u00eda; A. Hern\u00e1ndez.
\n\u00abXX Design of Integrated Circuits and Systems Conference.\u00bb. 2005.<\/p>\n

Analytical model for PN cross varactors<\/em><\/strong>
\nV Conferencia de Dispositivos Electr\u00f3nicos (Nacional)
\nTarragona, Espa\u00f1a, 2005
\nJ. A. P\u00e9rez; B. Gonz\u00e1lez; J. Garc\u00eda; J. del Pino; S. L. Khemchandani; A. Hern\u00e1ndez. \u00abV Conferencia de Dispositivos Electr\u00f3nicos\u00bb. 2005.<\/p>\n

DC Modeling of PN integrated cross varactors<\/em><\/strong>
\nSPIE – The International Society for Optical Engineering\u2019s International
\nSymposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference) Sevilla, Espa\u00f1a, 2005
\nB. Gonz\u00e1lez; J. A. P\u00e9rez; S. L. Khemchandani; A. Go\u00f1i; J. del Pino; J. Garc\u00eda. \u00abSPIE – The International Society for Optical Engineering\u2019s II International Symposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference) \u00ab. 2005.<\/p>\n

Design and modelling of an on silicon spiral inductors library using improved EM simulations<\/em><\/strong>
\nSPIE – The International Society for Optical Engineering\u2019s International
\nSymposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference) Sevilla, Espa\u00f1a, 2005
\nA. Go\u00f1i; S. L. Khemchandani; J. del Pino; J. Garc\u00eda; B. Gonz\u00e1lez; A. Hern\u00e1ndez. \u00abSPIE – The International Society for Optical Engineering\u2019s II International Symposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference)\u00bb. 2005.<\/p>\n

Integrated MOS Varactors in Accumulation Mode for RF Applications<\/em><\/strong>
\nXIX Design of Integrated Circuits and Systems Conference
\nBordeaux, Francia, 2004
\nB. Gonz\u00e1lez; J. Garc\u00eda; I. Gutierrez; N. Sainz; M. Marrero; A. Go\u00f1i; A. Hern\u00e1ndez.
\n\u00abXIX Design of Integrated Circuits and Systems Conference (Internacional\u00bb. 2004.<\/p>\n

A Simplified Physical Model for PN Junction Integrated Varactors<\/em><\/strong>
\nXVIII Design of Integrated Circuits and Systems Conference
\nCiudad Real, Espa\u00f1a, 2003
\nI. Guti\u00e9rrez; N. Sainz; J. Garc\u00eda; E. Hern\u00e1ndez; J. del Pino; B. Gonz\u00e1lez; J. Mel\u00e9ndez. \u00abXVIII Design of Integrated Circuits and Systems Conference.\u00bb. 2003.<\/p>\n

A Software for Varactors Simulation Based on Finite Difference Approximation<\/em><\/strong>
\nIV Conferencia de Dispositivos Electr\u00f3nicos
\nBarcelona, Espa\u00f1a, 2003
\nN. Sainz; I. Guti\u00e9rrez; J. Legarda; J. Garc\u00eda; J. de N\u00f3.
\n\u00abIV Conferencia de Dispositivos Electr\u00f3nicos\u00bb. 2003.<\/p>\n

DC – Extrinsic Model for AlGaAs\/InGaAs\/GaAs HFETs<\/em><\/strong>
\n12th European Workshop on Heterostructure Technology, MonD6
\nSegovia, Espa\u00f1a, 2003
\nB. Gonz\u00e1lez; A. Hern\u00e1ndez; J. Garc\u00eda; J. del Pino; J. R. Sendra; A. N\u00fa\u00f1ez. \u00ab12th European Workshop on Heterostructure Technology, MonD6\u00bb. 2003.<\/p>\n

Empirical model of the metal losses in integrated inductors<\/em><\/strong>
\nSPIE – The International Society for Optical Engineering\u2019s I International Symposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference)
\n(Internacional) Las Palmas, Espa\u00f1a, 2003
\nJ. del Pino; J. Garc\u00eda; B. Gonz\u00e1lez; J. R. Sendra; A. Hern\u00e1ndez; A. Garc\u00eda-Alonso; A. N\u00fa\u00f1ez. \u00abSPIE \u2013 The International Society for Optical Engineering\u2019s I International Symposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference)\u00bb. 2003.<\/p>\n

Integrated PN cross varactors for RF applications<\/em><\/strong>
\nXVIII Design of Integrated Circuits and Systems Conference
\nCiudad Real, Espa\u00f1a, 2003
\nJ. Garc\u00eda; B. Gonz\u00e1lez; J. del Pino; I. Guti\u00e9rrez; N. Sainz; J. R. Sendra; A. Hern\u00e1ndez; A. N\u00fa\u00f1ez.
\n\u00abXVIII Design of Integrated Circuits and Systems Conference.\u00bb. 2003.<\/p>\n

Interdigitated varactors for RFIC applications at different standard frequencies<\/em><\/strong>
\nIV Conferencia de Dispositivos Electr\u00f3nicos. Barcelona, Espa\u00f1a, 2003
\nI. Guti\u00e9rrez; J. Garc\u00eda; E. Hern\u00e1ndez; J. R. Sendra; J del Pino; J. Mel\u00e9ndez.
\n\u00abIV Conferencia de Dispositivos Electr\u00f3nicos\u00bb. 2003.<\/p>\n

PN Junction Integrated Varactors for RF Applications at Different Standard Frequencies<\/em><\/strong>
\nIEEE Conference IV Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Garmisch, Alemania, 2003
\nI. Guti\u00e9rrez; J. Garc\u00eda; N. Sainz; J. R. Sendra; J. de N\u00f3; A. Hern\u00e1ndez.
\n\u00abIEEE Conference IV Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF03\u00bb. 2003.<\/p>\n

PN Junction Integrated Varactors with Cross Structure<\/em><\/strong>
\nIV Conferencia de Dispositivos Electr\u00f3nicos. Barcelona, Espa\u00f1a, 2003
\nJ. Garc\u00eda; N. Sainz; B. Gonz\u00e1lez; J. Presa; A. Hern\u00e1ndez.
\n\u00abIV Conferencia de Dispositivos Electr\u00f3nicos\u00bb.2003.<\/p>\n

Temperature extrinsic modeling in HFETs<\/em><\/strong>
\nIV Conferencia de Dispositivos Electr\u00f3nicos. Barcelona, Espa\u00f1a, 2003
\nB. Gonz\u00e1lez; A. Hern\u00e1ndez; J. Garc\u00eda; J. del Pino; J. R. Sendra; A. N\u00fanez.
\n\u00abIV Conferencia de Dispositivos Electr\u00f3nicos\u00bb. 2003.<\/p>\n

Temperature in HFETs when operating in DC<\/em><\/strong>
\nSPIE – The International Society for Optical Engineering\u2019s I International Symposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference)
\nLas Palmas, Espa\u00f1a, 2003
\nB. Gonz\u00e1lez; A. Hern\u00e1ndez; J. Garc\u00eda; J. del Pino; J. R. Sendra; A. N\u00fa\u00f1ez.
\n\u00abSPIE – The International Society for Optical Engineering\u2019s I International Symposium on Microtechnologies for the New Millennium Design (VLSI Circuits and Systems Conference)\u00bb. 2003.<\/p>\n

The Impact of Integrated Inductors on Low Noise Amplifiers<\/em><\/strong>
\nXVIII Design of Integrated Circuits and Systems Conference
\nCiudad Real, Espa\u00f1a, 2003
\nJ. del Pino; S. L. Khemchandani; A. Hern\u00e1ndez; J. R. Sendra; J. Garc\u00eda; B. Gonz\u00e1lez; A. N\u00fa\u00f1ez.
\n\u00abXVIII Design of Integrated Circuits and Systems Conference.\u00bb. 2003.<\/p>\n

Automatic Timing Model Development for CMOS Logic Circuits<\/strong><\/em>
\nXVII Design of Integrated Circuits and Systems Conference. Santander, Espa\u00f1a, 2002
\nJ. Garc\u00eda; A. Hern\u00e1ndez; J. del Pino; B. Gonz\u00e1lez; J. R. Sendra; A. N\u00fa\u00f1ez.
\n\u00abXVII Design of Integrated Circuits and Systems Conference\u00bb. 2002.<\/p>\n

Discrimination of pigmented skin lesions by VIS-NIR spectrocopy: preliminary study<\/em><\/strong>
\nBiophotonics 2002 Heraklion, Grecia 2002
\nM. Cordo; J. R. Sendra; S.M. L\u00f3pez-Silva; J. Garc\u00eda; A. Viera.
\n\u00abProc. Biophotonics 2002\u00bb. 2002.<\/p>\n

Layout Constraints for RF Integrated Inductors on Silicon<\/em><\/strong>
\nXVII Design of Integrated Circuits and Systems Conference. Santander, Espa\u00f1a, 2002
\nJ. del Pino; J. Garc\u00eda; A. Hern\u00e1ndez; B. Gonz\u00e1lez; J. R. Sendra; A. N\u00fa\u00f1ez.
\n\u00abXVII Design of Integrated Circuits and Systems Conference\u00bb. 2002.<\/p>\n

On Silicon Integrated Inductor Library Design for Wireless Applications<\/em><\/strong>
\nXXVIII Conference of the IEEE Industrial Electronics Society (IECON\u201902) Sevilla, Espa\u00f1a, 2002
\nJ. del Pino; J. R. Sendra; A. Hern\u00e1ndez; J. Garc\u00eda; B. Gonz\u00e1lez; J. Aguilera; J. Hern\u00e1ndez; J. de N\u00f3; A.N\u00fa\u00f1ez.
\n\u00abXXVIII Conference of the IEEE Industrial Electronics Society (IECON\u201902)\u00bb. 2002.<\/p>\n

Temperature Behavior Modeling of Intrinsic InGaAs PHFET<\/strong><\/em>
\nXVII Design of Integrated Circuits and Systems Conference. Santander, Espa\u00f1a, 2002
\nB. Gonz\u00e1lez; J. Garc\u00eda; A. Hern\u00e1ndez; J. del Pino; J. R. Sendra; A. N\u00fa\u00f1ez.
\n\u00abXVII Design of Integrated Circuits and Systems Conference\u00bb. 2002.<\/p>\n

A 1.575 GHz SiGe Low Noise Amplifiers for GPS Applications<\/em><\/strong>
\nXVI Design Circuits and Integrated Systems Conference Oporto, Portugal 2001
\nJ. del Pino; S. L. Khemchandani; A. Hern\u00e1ndez; J. R. Sendra; J. Garc\u00eda; B. Gonz\u00e1lez; A. N\u00fa\u00f1ez.
\n\u00abXVI Design Circuits and Integrated Systems Conference,\u00bb. pp. 479 – 484. 2001.<\/p>\n

Modelling and Automatic Generation Tool for Integrated Inductors in CMOS Technology<\/em><\/strong>
\nXVI Design Circuits and Integrated Systems Conference Oporto, Portugal 2001
\nJ. del Pino; J. R. Sendra; A. Hern\u00e1ndez; S. L. Khemchandani; J. Aguilera; B. Gonz\u00e1lez; J. Garc\u00eda; A. N\u00fa\u00f1ez.
\n\u00abXVI Design Circuits and Integrated Systems Conference,\u00bb. pp. 378 – 383. 2001.<\/p>\n

SiDSen: A program to simulate delays based on sensitivity analysis model<\/strong><\/em>
\nXVI Design Circuits and Integrated Systems Conference Oporto, Portugal 2001
\nJ. Garc\u00eda; J. Pulido; A. Hern\u00e1ndez; J. del Pino; B. Gonz\u00e1lez; J. R. Sendra; A. N\u00fa\u00f1ez. \u00abXVI Design Circuits and Integrated Systems Conference,\u00bb. pp. 192 – 197. 2001.<\/p>\n

Fotopletismograf\u00eda y oximetr\u00eda de pulso mediante espectroscopia VIS-NIR<\/em><\/strong>
\nJornadas de Ingenier\u00eda M\u00e9dica en Canarias Las Palmas de Gran Canaria, Espa\u00f1a 2000
\nS. M. L\u00f3pez; J. R. Sendra; J. del Pino; J. Garc\u00eda; B. Gonz\u00e1lez; A. Hern\u00e1ndez. \u00abJornadas de Ingenier\u00eda M\u00e9dica en Canarias\u00bb. 2000<\/p>\n

Oximetr\u00eda in vivo mediante espectroscopia \u00f3ptica<\/em><\/strong>
\nJornadas de Ingenier\u00eda M\u00e9dica en Canarias Las Palmas de Gran Canaria, Espa\u00f1a 2000
\nS. M. L\u00f3pez; J. R. Sendra; J. del Pino; J. Garc\u00eda; B. Gonz\u00e1lez; A. Hern\u00e1ndez. \u00abJornadas de Ingenier\u00eda M\u00e9dica en Canarias\u00bb. 2000.<\/p>\n

Optimization of the delta-Doped Layer Concentration in P-HFETs at Medium\/High Temperatures<\/em><\/strong>
\nXIII Design of Integrated Circuits and Systems Conference Palma de Mallorca, Espa\u00f1a 1999
\nB. Gonz\u00e1lez; A. Hern\u00e1ndez; J. Garc\u00eda; J. del Pino; J. R. Sendra; A. N\u00fa\u00f1ez.
\n\u00abProceedings of the XIII Design of Integrated Circuits and Systems Conference, p\u00e1gs. 433-437\u00bb. 1999.<\/p>\n

Application of Sensitivity Analysis in Modelling Power and Delay for HFET DCFL Circuits<\/em><\/strong>
\nVIII International Symposium of Power and Timing Modelling Optimization and Simulation Lyngby, Dinamarca 1998
\nJ. Garc\u00eda; J. del Pino; B. Gonz\u00e1lez; A. Hern\u00e1ndez; A. N\u00fa\u00f1ez.
\n\u00abProceedings of the VIII International Symposium of Power and Timing Modelling Optimization and Simulation, p\u00e1gs. 51-60\u00bb. 1998.<\/p>\n

Efficient Transistor Count Reduction for a Low Power GaAs A\/D Converter<\/em><\/strong>
\nXIII Design Circuits and Integrated Systems Conference. Madrid, 1998
\nB. Gonz\u00e1lez; D. Abbot; Al-Sarawi; A. Hern\u00e1ndez; J. L\u00f3pez; J. Garc\u00eda. \u00abProceedings of the XIII Design Circuits and Integrated Systems Conference, 96-100\u00bb. 1998.<\/p>\n

Estimation of Power Consumption Based on Sensitivity Analysis for DCFL with HFET\u2019s<\/em><\/strong>
\nXIII Design Circuits and Integrated Systems Conference Madrid,1998
\nJ. Garc\u00eda; A. Hern\u00e1ndez; J. del Pino; B. Gonz\u00e1lez; A. N\u00fa\u00f1ez.
\n\u00abProceedings of the XIII Design Circuits and Integrated Systems Conference, 96-100\u00bb. 1998.<\/p>\n

Influence of temperature and doped layer concentration on P-HFETs<\/strong><\/em>
\nInternational Symposium on IC Technology, Systems & Applications.Singapore, 1997
\nB. Gonz\u00e1lez; A. Hern\u00e1ndez; J. Garc\u00eda; A. N\u00fa\u00f1ez.
\n\u00abProceedings of the XII Design of Circuits and Integrated Systems Conference, p\u00e1gs. 459-464\u00bb. 1997.<\/p>\n

Performance Analysis and Propagation Delay Time Estimation of Logic Families with HBTs<\/strong><\/em>
\nVII International Symposium of Power and Timing Modelling Optimization and Simulation. Lovain-la-Neuve, B\u00e9lgica 1997
\nJ. del Pino; A. Hern\u00e1ndez; B. Gonz\u00e1lez; J. Garc\u00eda; A. N\u00fa\u00f1ez.
\n\u00abProceedings of the VII International Symposium of Power and Timing Modelling Optimization and Simulation, p\u00e1gs. 323-332\u00bb. 1997.<\/p>\n

Performance Analysis and Propagation Delay Time Estimation of Logic Families with HBTs<\/strong><\/em>
\nXII Design of Circuits and Integrated Systems Conference Sevilla, Espa\u00f1a 1997
\nJ. del Pino; A. Hern\u00e1ndez; B. Gonz\u00e1lez; J. Garc\u00eda; A. N\u00fa\u00f1ez.
\n\u00abProceedings of the XII Design of Circuits and Integrated Systems Conference, p\u00e1gs. 459-464\u00bb. 1997.<\/p>\n

Timing Analysis Model Based on Sensitivity for DCFL Family with HFET\u2019s<\/em><\/strong>
\nXII Design of Circuits and Integrated Systems Conference Sevilla, Espa\u00f1a 1997
\nJ. Garc\u00eda; A. Hern\u00e1ndez; B. Gonz\u00e1lez; J. del Pino; A. N\u00fa\u00f1ez.
\n\u00abProceedings of the XII Design of Circuits and Integrated Systems Conference, p\u00e1gs. 453-457,\u00bb. 1997.<\/p>\n","protected":false},"excerpt":{"rendered":"

DC self-heating in GaN on Si MOS-HEMTs Workshop on Compound Semiconductor Devices and Integrated Circuits held in Europe. WOCSDICE 2017 Las Palmas de Gran Canaria, Espa\u00f1a Instituto Universitario de Microeelctr\u00f3nica Aplicada. Universidad de Las Palmas de Gran Canaria R. Rodr\u00edguez, B. Gonz\u00e1lez, J. Garc\u00eda and A. Nunez DC characteristics with substrate temperature for GaN on […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":18,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-49","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/wp-json\/wp\/v2\/pages\/49","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/wp-json\/wp\/v2\/comments?post=49"}],"version-history":[{"count":4,"href":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/wp-json\/wp\/v2\/pages\/49\/revisions"}],"predecessor-version":[{"id":94,"href":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/wp-json\/wp\/v2\/pages\/49\/revisions\/94"}],"up":[{"embeddable":true,"href":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/wp-json\/wp\/v2\/pages\/18"}],"wp:attachment":[{"href":"https:\/\/www.iuma.ulpgc.es\/jgarcia\/wp-json\/wp\/v2\/media?parent=49"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}