This work describes the design of a FPGA SoC that, integrated in a DAS module, provides a sixteen-channel simultaneous DAS that amplifies at different gains, captures at high speed (256 KSPS) and 24 bit resolution, adds Unix real-time stamps with second or millisecond resolution to the samples, averages the samples and sends the processed signals as binary files to a remote station via Ethernet. This FPGA-based DAS is controlled and configured via commands and an interactive configuration menu. In addition, it shuts down in a controlled manner in the event of a power failure.

• Presidente: Sebastián López Suárez
• Secretario: Alfonso Medina Escuela
• Vocal: Ernestina Martel Jordán