IUMA Seminar Series FPGA-Based Hardware Accelerators and Hybrid Systems
El próximo viernes 18 de marzo a las 9:30 en el Salón de Actos del Edificio de Electrónica y Telecomunicación, el Dr. Christian De Schryver -TU Kaiserslautern, Alemania impartirá un seminario sobre "Aceleradores hardware basados en FPGA y sistemas híbridos".
El seminario será en inglés con el siguiente contenido:
9:30 – 10:15. Unit 1: High-Level FPGA Design Tools
1. CHPC work and experience with Xilinx Vivado HLS, Xilinx SDAccel, and Maxeler OpenSPL.
2. Examples. Results and issues found while working with the tools. Comments on the state-of-production and how we would recommend the tools.
10:15 – 11:00. Unit 2: Hybrid Platform Design and the Agile FPGA Design Flow
1. Novel agile FPGA platform design flow.
2. Example: a hybrid platform for financial simulations.
3. Comparison against traditional FPGA design flow and comments on the pros and cons of our approach.
11:00 – 11:30. Break
11:30 – 12:30. Unit 3: Custom-Precision FPGA designs
1. CHPC work on custom-precision floating point data paths for FPGAs.
2. Methodology for optimizing precisions for a target result accuracy with an example application, and how to tune operators to those.
3. Ongoing and future work. Current research challenges in this domain.
12:30 – 13:30. Unit 4: Flexible RIVER Image Processing Platform
1. Hybrid CPU/FPGA image processing system for object detection (industry project).
2. Overview of the concept. Run-time flexibility introduced on various layers.
Póster Aceleradores hardware basados en FPGA y sistemas híbridos
Christian De Schryver graduated in Information Technology and received a PhD in Electrical Engineering, both from the University of Kaiserslautern, Germany. At this place, he is currently a Post-Doc and Senior Member of the Customized High Performance Computing (CHPC) research team within the Microelectronic Systems Design Research Group headed by Prof. Dr. Norbert Wehn. His research interests are design methodologies for application-tailored heterogeneous execution platforms, hardware accelerators for supercomputing applications (in particular finance and big data processing), and system-level design flows.