IUMA is present at the N2 technology presentation workshop at IMEC

Last June, IUMA researcher Pedro Pérez Carballo attended the "Advanced PDK Workshop: N2 Nanosheet Pathfinding and Applications" at IMEC, Leuven. In this workshop, an advanced experimental N2 (2 nm) technology has been presented, which has been developed at IMEC to provide an evaluation platform for the implementation of complex system-on-chip architectures.

The idea is that this design kit allows to analyse the ease of scaling to advanced nodes of current architectural solutions, facilitating the early detection of architectural bottlenecks with respect to technological scaling, applying the concept of System-Technology Co-Optimization (STCO) versus the traditional Design-Technology Co-Optimization (DTCO).

The technology includes transistors based on nanosheets, with Gate All Around Architecture (GAA) and powered at the back of the device BSPDN (BackSide Power Delivery Network). Both p and n transistors have been used to create libraries of standard cells and SRAM memory cells.

This action is supported by the project NanoIC pilot line led by IMEC (Belgium), with partners CEA-Leti (France), Fraunhofer (Germany), VTT (Finland), CSSNT (Romania), and Tyndall National Institute (Ireland), supported by Chips JU and under the umbrella of the European Chips Act.

The workshop was attended by 60 people on the first day of technology presentations and culminated with a visit to the IMEC Foundry. The second day was dedicated to practical sessions on the use of the standard cell libraries with Cadence and Synopsys, which was attended by 20 researchers.

For more information:

• Imec launches the first design pathfinding process design kit for N2 node
• Unlocking tomorrow’s technology nodes: inside imec’s N2 P-PDK workshop
• Linkedin post about the workshop

Workshop attendees (IMEC)